HD64F2328VTE25 Datasheet, PDF (730/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 ROM
There are two memory MATs: user MAT and user boot MAT. The dedicated registers/parameters
are allocated for each operating mode and MAT selection. The correspondence of operating modes
and registers/parameters for use is shown in table 17.49.
Table 17.48 (1) Register Configuration
Name
Flash code control status register
Abbreviation
FCCS
R/W
R, W^*1
Initial Value
H'00
H'80
Address
H'FFC4
Flash program code select register
FPCS
R/W H'00
H'FFC5
Flash erase code select register
FECS
R/W H'00
H'FFC6
Flash key code register
Flash MAT select register
FKEY
FMATS
R/W H'00
R/W
H'00^*2
H'AA^*2
H'FFC8
H'FFC9
Flash transfer destination address
register
System control register 2
FTDAR
R/W H'00
SYSCR2^*3
R/W
H'00
H'FFCA
H'FF42
RAM emulation register
RAMER
R/W H'00
H'FEDB
Notes: 1. The bits except the SCO bit are read-only bits. The SCO bit is a programming-only bit.
(The value which can be read is always 0.)
2. The initial value at initiation in user mode or user program mode is H'00.
The initial value at initiation in user boot mode is H'AA.
3. SYSCR2 is dedicated to the F-ZTAT versions.
Table 17.48 (2) Parameter Configuration
Name
Download pass/fail result
Abbreviation R/W
DPFR
R/W
Initial Value Address
Undefined
On-chip RAM^*
Flash pass/fail result
FPFR
R/W
Undefined
R0L of CPU
Flash multipurpose address area
FMPAR
R/W
Undefined
ER1 of CPU
Flash multipurpose data destination FMPDR
area
R/W
Undefined
ER0 of CPU
Flash erase block select
FEBS
R/W
Undefined
ER0 of CPU
Flash program and erase frequency FPEFEQ
control
R/W Undefined
ER0 of CPU
Note: * One byte of the start address in the on-chip RAM area specified by FTDAR is valid.
Rev.7.00 Feb. 14, 2007 page 696 of 1108
REJ09B0089-0700