S7G2 Datasheet, PDF (77/116 Pages) Renesas Technology Corp – 32-bit ARM Cortex-M4 microcontroller

S7G2
2. Electrical Characteristics
Table 2.27 IIC timing (1) (2/2)
Conditions: Middle drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: SDA0_B, SCL0_B,
SDA1_A, SCL1_A, SDA1_B, SCL1_B.
The following pins do not require setting: SCL0_A, SDA0_A, SCL2, SDA2.
Item
IIC
(Fast mode)
SCL input cycle time
SCL input high pulse width
SCL input low pulse width
SCL, SDA input rise time
SCL, SDA input fall time
SCL, SDA input spike pulse removal
time
SDA input bus free time when
wakeup function is disabled
SDA input bus free time when
wakeup function is enabled
START condition input hold time
when wakeup function is disabled
START condition input hold time
when wakeup function is enabled
Repeated START condition input
setup time
STOP condition input setup time
Data input setup time
Data input hold time
SCL, SDA capacitive load
Symbol Min*¹, *²
t_SCL
t_SCLH
t_SCLL
t_Sr
6 (12) × t_IICcyc + 600
3 (6) × t_IICcyc + 300
3 (6) × t_IICcyc + 300
20 × (external pullup
voltage/5.5V)*²
t_Sf
20 × (external pullup
voltage/5.5V)*²
t_SP
0
t_BUF
3 (6) × t_IICcyc + 300
t_BUF
t_STAH
3 (6) × t_IICcyc + 4 × t_Pcyc
+ 300
t_IICcyc + 300
t_STAH
t_STAS
1(5) × t_IICcyc + t_Pcyc +
300
300
t_STOS
t_SDAS
t_SDAH
C_b
300
t_IICcyc + 50
0
-
Max
-
-
-
300
300
1 (4) × t_IICcyc
-
-
-
-
-
-
-
-
400
Test
Unit conditions
ns Figure 2.52
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
Note: t_IICcyc: IIC internal reference clock (IICφ) cycle, t_Pcyc: PCLKB cycle.
Note 1. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE
set to 1.
Note 2. Only supported for SCL0_A, SDA0_A, SCL2, and SDA2.
R01DS0262EU0100 Rev.1.00
Feb 23, 2016
Page 77 of 113