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S7G2 Datasheet, PDF (71/116 Pages) Renesas Technology Corp – 32-bit ARM Cortex-M4 microcontroller
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S7G2
2.3.11
SPI Timing
2. Electrical Characteristics
Table 2.25 SPI timing
Conditions:
(1) Middle drive output is selected with the port drive capability bit in the PmnPFS register.
(2) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the SPI interface,
the AC portion of the electrical characteristics is measured for each group.
Item
Symbol Min
Max
Unit*1 Test conditions
SPI
RSPCK clock cycle
Master
tSPcyc
2 (PCLKA  60 MHz)
4 (PCLKA > 60 MHz)
4096
tPcyc
Figure 2.43
C = 30 pF
Slave
6
4096
RSPCK clock high
Master
tSPCKWH (tSPcyc – tSPCKR – tSPCKF) / 2 – 3 -
ns
pulse width
Slave
3 × tPcyc
-
RSPCK clock low pulse Master
tSPCKWL (tSPcyc – tSPCKR – tSPCKF) / 2 – 3 -
ns
width
Slave
3 × tPcyc
-
RSPCK clock rise and Master
fall time
Slave
tSPCKr,
-
tSPCKf
-
5
ns
1
µs
Data input setup time
Data input hold time
SSL setup time
Master
Slave
Master
Master
Slave
Master
tSU
tHF*4
tH
tH
tLEAD
4
5
0
tPcyc
20
N × tSPcyc - 10*2
-
ns
-
-
ns
-
-
N×
ns
tSPcyc +
100 *2
Figure 2.44 to
Figure 2.49
C = 30 pF
-
-
-
SSL hold time
Slave
Master
tLAG
6 x tPcyc
N × tSPcyc - 10 *3
-
ns
-
N×
ns
-
tSPcyc +
100 *3
Slave
Data output delay
Master
tOD
Slave
Data output hold time Master
tOH
Slave
6 x tPcyc
-
-
0
0
-
ns
-
6.3
ns
Figure 2.44 to
20
Figure 2.49
C = 30PF
-
ns
-
Successive
transmission delay
Master
MOSI and MISO rise
and fall time
Slave
Output
Input
tTD
tDr, tDf
tSPcyc + 2 × tPcyc
6 × tPcyc
-
-
8×
ns
tSPcyc +
2 × tPcyc
5
ns
1
μs
SSL rise and fall time Output
tSSLr,
-
Input
tSSLf
-
5
ns
1
μs
Slave access time
Slave output release time
tSA
-
tREL
-
2 x tPcyc ns
+ 28
2 x tPcyc
+ 28
Figure 2.48 and
Figure 2.49
C = 30PF
Note 1. tPcyc: PCLKA cycle.
Note 2. N is set to an integer from 1 to 8 by the SPCKD register.
Note 3. N is set to an integer from 1 to 8 by the SSLND register.
Note 4. PCLKA division ratio set to 1/2.
R01DS0262EU0100 Rev.1.00
Feb 23, 2016
Page 71 of 113
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