HD404339 Datasheet, PDF (75/80 Pages) Hitachi Semiconductor – 4-bit HMCS400-Series microcomputer with large-capacity memory

HD404339 Series
a. After V_CC reaches 4.0 V at power-on.
b. After RESET input goes low when stop mode is cancelled.
c. After STOPC input goes low when stop mode is cancelled.
To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET
or STOPC must be input for at least a duration of t_RC.
When using a crystal or ceramic oscillator, consult with the manufacturer to determine what
stabilization time is required, since it will depend on the circuit constants and stray capacitance.
3. Refer to figure 56.
4. Refer to figure 57.
5. Refer to figure 58.
6. Refer to figure 59.
7. Applies to the HD404334, HD404336, HD404338, HD4043312, and HD404339.
8. Applies to the HD4074339.
Serial Interface Timing Characteristics (V_CC = 4.0 to 5.5 V, GND = 0 V, V_disp = V_CC – 40 V to V_CC, T_a =
–20 to +75°C, unless otherwise specified)
During Transmit Clock Output
Item
Transmit clock cycle time
Transmit clock high width
Transmit clock low width
Transmit clock rise time
Transmit clock fall time
Serial output data delay time
Serial input data setup time
Serial input data hold time
Symbol Pins
t _Scyc
t _SCKH
t _SCKL
t _SCKr
t _SCKf
SCK
SCK
SCK
SCK
SCK
t _DSO
SO
t _SSI
SI
t _HSI
SI
Min Typ Max Unit Test Condition
1 — — t_cyc Load shown in figure 61
0.4 — — t_Scyc Load shown in figure 61
0.4 — — t_Scyc Load shown in figure 61
— — 80 ns Load shown in figure 61
— — 80 ns Load shown in figure 61
— — 300 ns Load shown in figure 61
100 — — ns
200 — — ns
Note
1
1
1
1
1
1
1
1
During Transmit Clock Input
Item
Symbol
Transmit clock cycle time
t _Scyc
Transmit clock high width
t _SCKH
Transmit clock low width
t _SCKL
Transmit clock rise time
t _SCKr
Transmit clock fall time
t _SCKf
Serial output data delay time t_DSO
Serial input data setup time t_SSI
Serial input data hold time t_HSI
Note: 1. Refer to figure 60.
Pins
SCK
SCK
SCK
SCK
SCK
SO
SI
SI
Min Typ Max Unit Test Condition
1
— — t_cyc
0.4 — — t_Scyc
0.4 — — t_Scyc
— — 80 ns
— — 80 ns
— — 300 ns Load shown in figure 61
100 — — ns
200 — — ns
Note
1
1
1
1
1
1
1
1
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