HD404339 Datasheet, PDF (23/80 Pages) Hitachi Semiconductor – 4-bit HMCS400-Series microcomputer with large-capacity memory

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In stop mode, the system oscillator is stopped. To ensure a proper oscillation stabilization period of at least
t_RC when clearing stop mode, execute the cancellation according to the timing chart in figure 12.
In watch and subactive modes, a timer A or INT₀ interrupt can be accepted during the interrupt frame
period T (see figure 13).
Note:
In watch and subactive modes, an interrupt will not be properly detected if the INT₀ high or low
level period is shorter than the interrupt frame period T. Thus, when operating in watch and
subactive modes, maintain the INT₀ high or low level period longer than period T to ensure
interrupt detection.
Oscillator
Internal
clock
Stop mode
RESET
or
STOPC
STOP instruction execution
t_res
t_res ≥ t_RC (stabilization period)
Figure 12 Timing of Stop Mode Cancellation
Active mode
Watch mode
Oscillation
stabilization
period
Active mode
Interrupt strobe
INT₀
Interrupt request
generation
(During the transition
from watch mode to
active mode only)
T
T
t _RC
Tx
T + t_RC ≤ T_X ≤ 2T + t_RC
T: Interrupt frame length
t _RC : Oscillation stabilization period
Figure 13 Interrupt Frame
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