16C6N5 Datasheet, PDF (75/88 Pages) Renesas Technology Corp – Renesas MCU

Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Switching Characteristics
VCC = 3.3 V
(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.68 Memory Expansion Mode and Microprocessor Mode
(for 2- to 3-wait setting, external area access and multiplexed bus selection)
Symbol
Parameter
Measuring
Condition
Standard
Min.
Max.
Unit
td(BCLK-AD) Address output delay time
Figure 5.21
50
ns
th(BCLK-AD) Address output hold time (in relation to BCLK)
4
ns
th(RD-AD) Address output hold time (in relation to RD)
(NOTE 1)
ns
th(WR-AD) Address output hold time (in relation to WR)
(NOTE 1)
ns
td(BCLK-CS) Chip select output delay time
50
ns
th(BCLK-CS) Chip select output hold time (in relation to BCLK)
4
ns
th(RD-CS) Chip select output hold time (in relation to RD)
(NOTE 1)
ns
th(WR-CS) Chip select output hold time (in relation to WR)
(NOTE 1)
ns
td(BCLK-RD) RD signal output delay time
40
ns
th(BCLK-RD) RD signal output hold time
0
ns
td(BCLK-WR) WR signal output delay time
40
ns
th(BCLK-WR) WR signal output hold time
0
ns
td(BCLK-DB) Data output delay time (in relation to BCLK)
50
ns
th(BCLK-DB) Data output hold time (in relation to BCLK)
4
ns
td(DB-WR) Data output delay time (in relation to WR)
(NOTE 2)
ns
th(WR-DB) Data output hold time (in relation to WR)
__________
td(BCLK-HLDA) HLDA output delay time
(NOTE 1)
ns
40
ns
td(BCLK-ALE) ALE signal output delay time (in relation to BCLK)
25
ns
th(BCLK-ALE) ALE signal output hold time (in relation to BCLK)
–4
ns
td(AD-ALE) ALE signal output delay time (in relation to Address)
(NOTE 3)
ns
th(ALE-AD) ALE signal output hold time (in relation to Address)
(NOTE 4)
ns
td(AD-RD) RD signal output delay from the end of Address
0
ns
td(AD-WR) WR signal output delay from the end of Address
0
ns
tdZ(RD-AD) Address output floating start time
8
ns
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 10⁹ _{– 10 [ns]}
f(BCLK)
2. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 10⁹
– 50 [ns]
f(BCLK)
n is “2” for 2-wait setting, “3” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
0.5 ✕ 10⁹ _{– 40 [ns]}
f(BCLK)
4. Calculated according to the BCLK frequency as follows:
0.5 ✕ 10⁹ _{– 15 [ns]}
f(BCLK)
Rev.2.40 Aug 25, 2006 page 75 of 84
REJ03B0004-0240