16C6N5 Datasheet, PDF (65/88 Pages) Renesas Technology Corp – Renesas MCU

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M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Memory Expansion Mode and Microprocessor Mode
(For 2-wait setting and external area access)
Read timing
tcyc
BCLK
CSi
ADi
BHE
ALE
td(BCLK-CS)
25ns.max
td(BCLK-AD)
25ns.max
td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
-4ns.min
th(BCLK-CS)
4ns.min
th(BCLK-AD)
4ns.min
th(RD-AD)
0ns.min
RD
DBi
Hi-Z
Write timing
BCLK
td(BCLK-RD)
25ns.max
tac2(RD-DB)
(2.5 ✕ tcyc-45)ns.max
tSU(DB-RD)
40ns.min
tcyc
th(BCLK-RD)
0ns.min
th(RD-DB)
0ns.min
CSi
ADi
BHE
ALE
td(BCLK-CS)
25ns.max
td(BCLK-AD)
25ns.max
td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
-4ns.min
th(BCLK-CS)
4ns.min
th(BCLK-AD)
4ns.min
th(WR-AD)
(0.5 ✕ tcyc-10)ns.min
WR, WRL
WRH
DBi
td(BCLK-WR)
25ns.max
td(BCLK-DB)
40ns.max
Hi-Z
th(BCLK-WR)
0ns.min
th(BCLK-DB)
4ns.min
tcyc = ¹
f(BCLK)
td(DB-WR)
(1.5 ✕ tcyc-40)ns.min
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
th(WR-DB)
(0.5 ✕ tcyc-10)ns.min
Figure 5.17 Timing Diagram (5)
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 65 of 84
REJ03B0004-0240