32171 Datasheet, PDF (743/772 Pages) Renesas Technology Corp – 32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES

Appendix 4
SUMMARY OF PRECAUTIONS
Appendix 4.8 Precautions on Multijunction Timers
Appendix 4.8 Precautions on Multijunction Timers
Appendix 4.8.1 Precautions to be observed when using TOP single-shot output mode
The following describes precautions to be observed when using TOP single-shot output mode.
• If the counter stops due to underflow in the same clock period as the timer is enabled by
external input, the former has priority (so that the counter stops).
• If the counter stops due to underflow in the same clock period as count is enabled by writing to
the enable bit, the latter has priority (so that count is enabled).
• If the timer is enabled by external input in the same clock period as count is disabled by writing
to the enable bit, the latter has priority (so that count is disabled).
• Because the internal circuit operation is synchronized to the count clock (prescaler output), a
finite time equal to a prescaler delay is included before F/F starts operating after the timer is
enabled.
Write to enable bit
Internal clock
Count clock
Enable
F/F operation
Prescaler cycle
Delay till prescaler
cycle
Figure A4.8.1 Prescaler Delay
• When writing to the correction register, be careful not to cause the counter to overflow. Even
when the counter overflows due to correction of counts, no interrupt is generated for the
occurrence of overflow. When the counter underflows in the subsequent down-count after
overflow, a false underflow interrupt is generated due to overcounting.
In the example below, the reload register has the initial value H'FFF8 set in it. When the timer
starts, the reload register value is loaded into the counter causing it to start counting down. In the
example diagram here, H'0014 is written to the correction register when the counter has counted
down to H'FFF0. As a result of this correction, the count overflows to H'0004 and fails to count
correctly. Also, an interrupt is generated for an erroneous overcount.
Appendix 4-7 32171 Group User's Manual (Rev.2.00)