32171 Datasheet, PDF (483/772 Pages) Renesas Technology Corp – 32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES

12
SERIAL I/O
12.4 Receive Operation in CSIO Mode
12.4.5 Flags Indicating the Status of CSIO Receive Operation
Following flags are available that indicate the status of receive operation in CSIO mode.
• SIO Receive Control Register receive status bit
• SIO Receive Control Register receive-finished bit
• SIO Receive Control Register receive error sum bit
• SIO Receive Control Register overrun error bit
After reception is completed, you may read out the content of the SIO Receive Buffer Register, but
if the serial I/O finishes receiving the next data before you read, an overrun error occurs. In this
case, the data received thereafter is not transferred to the SIO Receive Buffer Register. To restart
reception, temporarily clear the receive enable bit to 0 and initialize the receive control block before
you restart.
The said receive enable bit can be cleared, when there are no receive errors (Note 1) encountered,
by reading the lower byte from the SIO Receive Buffer Register or clearing the REN (receive
enable) bit. If any receive error has occurred, it can only be cleared by clearing the REN (receive
enable) bit, and cannot be cleared by reading the lower byte from the SIO Receive Buffer Register.
Note 1: Overrun error is the only error that can be detected during reception in CSIO mode.
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32171 Group User's Manual (Rev.2.00)