SH74572_15 Datasheet, PDF (7/13 Pages) Renesas Technology Corp – RENESAS MCU

SH74572
Appendix D
Appendix D
Section15 Interrupt Controller (INTC)
15.5 Interrupt Response Time
Table 15.9 shows the interrupt response time, which is the interval from when an interrupt request
occurs until the interrupt exception handling is started and the start instruction of the interrupt
handling is fetched.
Table 15.9 Interrupt Response Time
Item
Priority determination time
Wait time until the CPU finishes the
current sequence
Interval from when interrupt exception
handling begins (saving SR and PC) until
a SHwy bus request is issued to fetch the
start instruction of the interrupt handling
Response time
Total
Minimum
NMI
7 Pcyc
(S + 10) Icyc
+ 1Scyc + 7 Pcyc
55Icyc + S × Icyc
Legend:
Icyc: Period for one CPU clock cycle
Scyc: Period for one SHwy clock cycle
Pcyc: Period for one peripheral clock cycle
S: Number of instruction execution states
Number of State
Peripheral
IRQ
Module
6 Pcyc
5Pcyc
S-1 (≥ 0) × Icyc
11Icyc + 1Scyc
(S + 10) Icyc
+ 1Scyc + 6 Pcyc
49Icyc + S × Icyc
(S + 10) Icyc
+ 1Scyc + 5Pcyc
43Icyc + S × Icyc
Remarks
When
Icyc:Scyc:
Pcyc = 6:2:1
R01DS0189EJ0120 Rev.01.20
Sep 10, 2012
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