M37753M6C-XXXFP Datasheet, PDF (7/13 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M37753M6C-XXXFP, M37753M6C-XXXHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
BASIC FUNCTION BLOCKS
The M37753M6C-XXXFP and M37753M6C-XXXHP has the same
functions as the M37753M8C-XXXFP and M37753M8C-XXXHP ex-
cept for the following:
(1) The ROM size is different.
(2) The function of ROM area modification is not available.
Therefore, refer to the section on the M37753M8C-XXXFP.
MEMORY
The memory map is shown in Figure 1. The address space is 16
Mbytes from addresses 016 to FFFFFF16. The address space is di-
vided into 64-Kbyte units called banks. The banks are numbered
from 016 to FF16.
Internal ROM, internal RAM, and control registers for internal periph-
eral devices are assigned to bank 016.
The 48-Kbyte area from addresses 400016 to FFFF16 is the internal
ROM.
Addresses FFD216 to FFFF16 are the RESET and interrupt vector
addresses and contain the interrupt vectors. Refer to the section on
interrupts for details.
The 2048-byte area from addresses 8016 to 87F16 contains the in-
ternal RAM. In addition to storing data, the RAM is used as stack dur-
ing a subroutine call, or interrupts.
Assigned to addresses 016 to 7F16 are peripheral devices such as
I/O ports, A-D converter, D-A converter, UART, timer, and interrupt
control registers.
A 256-byte direct page area can be allocated anywhere in bank 016
using the direct page register DPR. In direct page addressing mode,
the memory in the direct page area can be accessed with two words
thus reducing program steps.
Bank 016
Bank 116
•
•
 ^00000016







 00FFFF16
 ^01000016







 _01FFFF16
•
•
•
•
•
•
•
•
•
•
•
 ^FE000016



Bank FE16 



 FEFFFF16
 ^FF000016



Bank FF16 



 FFFFFF16
00000016
00007F16
00008016
00087F16
Internal RAM
2048 bytes
00400016
Internal ROM
48 Kbytes
00FFFF16
00000016
00007F16
Peripherai devices
control registers
see Fig. 2 for
further information
Interrupt vector table
00FFD216
INT4
INT3
A-D
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT2
INT1
INT0
Watchdog timer
DBC
BRK instruction
00FFFE16
Zero divide
RESET
Fig. 1 Memory map
6