HD74LV166A_15 Datasheet, PDF (7/10 Pages) Renesas Technology Corp – Parallel-Load 8-bit Shift Register

HD74LV166A
Preliminary
Switching Characteristics (cont)
Item
Maximum clock
frequency
Propagation
delay time
Setup time
Hold time
Pulse width
Symbol
fmax
t_PLH/t_PHL
t_PHL
t_su
t_h
t_w
Ta = 25°C
Min Typ Max
110 165 —
95 125 —
— 6.0 9.9
— 7.7 11.9
— 5.4 8.6
— 6.9 10.6
3.5 — —
3.5 — —
4.5 — —
4.0 — —
4.0 — —
1.0 — —
1.0 — —
1.0 — —
5.0 — —
4.0 — —
Ta = –40 to 85°C
Min Max
90
—
85
—
1.0
11.5
1.0
13.5
1.0
10.0
1.0
12.0
3.5
—
3.5
—
4.5
—
4.0
—
4.0
—
1.0
—
1.0
—
1.0
—
5.0
—
4.0
—
Unit
MHz
ns
ns
ns
ns
Test
Conditions
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
(V_CC = 5.0 ± 0.5 V)
FROM
TO
(Input) (Output)
CLK
Q_H
CLR
CLR inactive before
CLK 
CLK INH before CLK 
Data before CLK 
SH/LD high before CLK

SER before CLK 
PAR data after SH/LD 
SER data after CLK 
SH/LD high after CLK 
CLR low
CLK H or L
Operating Characteristics
Item
Power dissipation capacitance
Symbol
C_PD
V_CC (V)
3.3
5.0
Ta = 25°C
Min
Typ
Max
—
36.1
—
—
37.5
—
(C_L = 50 pF)
Unit Test Conditions
pF f = 10 MHz
Test Circuit
Measurement point
C_L*
Note: C_L includes the probe and jig capacitance.
R04DS0002EJ0400 Rev.4.00
Aug 16, 2010
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