HD74LV166A_15 Datasheet, PDF (6/10 Pages) Renesas Technology Corp – Parallel-Load 8-bit Shift Register

HD74LV166A
Preliminary
Switching Characteristics
Item
Maximum clock
frequency
Propagation
delay time
Setup time
Hold time
Pulse width
Symbol
fmax
t_PLH/t_PHL
t_PHL
t_su
t_h
t_w
Ta = 25°C
Min Typ Max
50 80 —
40 65 —
— 12.2 19.8
— 15.3 23.3
— 10.8 16.0
— 14.2 19.5
6.0 — —
7.0 — —
6.5 — —
7.0 — —
8.5 — —
–0.5 — —
–0.5 — —
–0.5 — —
8.0 — —
8.5 — —
Ta = –40 to 85°C
Min Max
45
—
35
—
1.0
22.0
1.0
26.0
1.0
18.0
1.0
22.0
7.0
—
7.0
—
8.5
—
8.5
—
9.5
—
0.0
—
0.0
—
0.0
—
9.0
—
9.0
—
Unit
MHz
ns
ns
ns
ns
Test
Conditions
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
(V_CC = 2.5 ± 0.2 V)
FROM
TO
(Input) (Output)
CLK
Q_H
CLR
CLR inactive before CLK

CLK INH before CLK 
Data before CLK 
SH/LD high before CLK

SER before CLK 
PAR data after SH/LD 
SER data after CLK 
SH/LD high after CLK 
CLR low
CLK H or L
Item
Maximum clock
frequency
Propagation
delay time
Symbol
fmax
t_PLH/t_PHL
t_PHL
Setup time
t_su
Hold time
t_h
Pulse width
t_w
Ta = 25°C
Min Typ Max
65 115 —
60 90 —
— 8.6 15.4
— 10.9 18.9
— 7.9 12.5
— 10.4 16.3
4.0 — —
5.0 — —
5.0 — —
5.0 — —
5.0 — —
0.0 — —
0.0 — —
0.0 — —
6.0 — —
6.0 — —
Ta = –40 to 85°C
Min Max
55
—
50
—
1.0
18.0
1.0
21.5
1.0
15.0
1.0
18.5
4.0
—
5.0
—
6.0
—
6.0
—
6.0
—
0.0
—
0.0
—
0.0
—
7.0
—
7.0
—
Unit
MHz
ns
ns
ns
ns
Test
Conditions
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
(V_CC = 3.3 ± 0.3 V)
FROM
TO
(Input) (Output)
CLK
Q_H
CLR
CLR inactive before
CLK 
CLK INH before CLK 
Data before CLK 
SH/LD high before CLK

SER before CLK 
PAR data after SH/LD 
SER data after CLK 
SH/LD high after CLK 
CLR low
CLK H or L
R04DS0002EJ0400 Rev.4.00
Aug 16, 2010
Page 6 of 9