HD74LV166A_15 Datasheet, PDF (1/10 Pages) Renesas Technology Corp – Parallel-Load 8-bit Shift Register

Preliminary Datasheet
HD74LV166A
Parallel-Load 8-bit Shift Register
R04DS0002EJ0400
(Previous: REJ03D0321-0300)
Rev.4.00
Aug 16, 2010
Description
The HD74LV166A is 8-bit shift register with an output from the last stage. Data may be loaded into the register either
in parallel or in serial form. When the Shift/Load input is low, the data is loaded asynchronously in parallel. When the
Shift/Load input is high, the data is loaded serially on the rising edge of either clock inhibit or Clock. Clear is
asynchronous and active-low.
The 2-input NOR clock may be used either by combining two independent clock sources or by designating one of the
clock inputs to act as a clock inhibit.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the
low-power consumption extends the battery life.
Features
 V_CC = 2.0 V to 5.5 V operation
 All inputs V_IH (Max.) = 5.5 V (@V_CC = 0 V to 5.5 V)
 All outputs V_O (Max.) = 5.5 V (@V_CC = 0 V)
 Typical V_OL ground bounce < 0.8 V (@V_CC = 3.3 V, Ta = 25°C)
 Typical V_OH undershoot > 2.3 V (@V_CC = 3.3 V, Ta = 25°C)
 Output current ±6 mA (@V_CC = 3.0 V to 3.6 V), ±12 mA (@V_CC = 4.5 V to 5.5 V)
 Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74LV166AFPEL
SOP–16 pin(JEITA)
PRSP0016DH-B FP
(FP–16DAV)
HD74LV166ATELL
TSSOP–16 pin
PTSP0016JB-A T
(TTP–16DAV)
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
ELL (2,000 pcs/reel)
Function Table
CLR
SH/LD
Inputs
CLK INH
CLK
SER
A ... H
Internal outputs
QA
QB
L
X
X
X
X
X
L
L
H
X
L
L
X
X
Q_A0
Q_B0
H
L
L

X
a ... h
a
b
H
H
L

H
X
H
Q_An
H
H
L

L
X
L
Q_An
H
X
H

X
X
Q_A0
Q_B0
Note: H: High level
L: Low level
: Low to high transition
X: Immaterial
a ... h: Parallel data
Q_A0 ... Q_H0: Outputs remain unchanged.
Q_An ... Q_Gn: Data shifted from the previous stage on a positive edge at the clock input.
Output
QH
L
Q_H0
h
Q_Gn
Q_Gn
Q_H0
R04DS0002EJ0400 Rev.4.00
Aug 16, 2010
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