HAT2033R_15 Datasheet, PDF (7/10 Pages) Renesas Technology Corp – Silicon N Channel Power MOS FET High Speed Power Switching

HAT2033R, HAT2033RJ
Reverse Drain Current vs.
Source to Drain Voltage
20
16
10 V
12
5V
8
V_GS = 0, –5 V
Maximum Avalanche Energy vs.
Channel Temperature Derating
5
I_AP = 7 A
V_DD = 25 V
4
L = 100 µH
duty < 0.1 %
Rg ≥ 50 Ω
3
2
4
1
Pulse Test
0
0 0.4 0.8 1.2 1.6 2.0
Source to Drain Voltage V_SD (V)
0
25 50 75 100 125 150
Channel Temperature Tch (°C)
Normalized Transient Thermal Impedance vs. Pulse Width (1 Drive Operation)
10
Vin
15 V
D=1
1
0.5
0.2
0.1 _0.1
0.05
0.02
0.01 _0.01
0.001
1shot ^pulse
0.0001
10 µ 100 µ 1 m
Avalanche Test Circuit
θch – f (t) = γ s (t) • θch – f
θch – f = 83.3°C/W, Ta = 25°C
When using the glass epoxy board
(FR4 40 × 40 × 1.6 mm)
P_DM
D = ^PW
T
PW
T
10 m 100 m 1
10
Pulse Width PW (S)
100 1000 10000
Avalanche Waveform
V_DS
Monitor
Rg
50 Ω
L
I_AP
Monitor
D.U.T
V_DD
E_AR =
1
2
• L • I_AP2 •
V_DSS
V_DSS – V_DD
I_AP
I_D
V_(BR)DSS
V_DS
V_DD
0
Rev.4.00 Sep 07, 2005 page 5 of 7