HD404054 Datasheet, PDF (69/103 Pages) Hitachi Semiconductor – HMCS400-series microcomputers designed to increase program productivity with large-capacity memory

HD404054 Series/HD404094 Series
In transfer state, writing data to serial mode register 1A (SM1A: $005) (06, 16) initializes serial
interface 1, and STS wait state is entered.
If the state changes from transfer to another state, the serial 1 interrupt request flag (IFS1: $003, bit 2) is
set by the octal counter that is reset to 000.
• Continuous clock output state (only in internal clock mode): Continuous clock output state is entered
only in internal clock mode. In this state, the serial interface does not transmit/receive data but only
outputs the transmit clock from the SCK₁ pin.
When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock
wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state.
If serial mode register 1A (SM1A: $005) is written to in continuous clock output mode (18), STS wait
state is entered.
External clock mode
STS wait state
(Octal counter = 000,
transmit clock disabled)
00 MCU reset
SM1A write 04
01 STS instruction
06 SM1A write (IFS1 ^← 1)
Transmit clock wait state
(Octal counter = 000)
02 Transmit clock
03
05
8 transmit clocks STS instruction (IFS1 ← 1)
Transfer state
(Octal counter ≠ 000)
Internal clock mode
SM1A write
18
STS wait state
(Octal counter = 000,
transmit clock disabled)
10 MCU reset
Continuous transmit
clock output state
(PMRA 0, 1 = 0, 0)
SM1A write 14
11 STS instruction
13 8 transmit clocks
16 SM1A write (IFS1← 1)
Transmit clock 17
Transmit clock wait state
(Octal counter = 000)
12 Transmit clock
15
STS instruction (IFS1← 1)
Transfer state
(Octal counter ≠ 000)
Note: Refer to the Operating States section for the corresponding encircled numbers.
Figure 50 Serial Interface State Transitions
Output Level Control in Idle States: When serial interface 1 is in STS instruction wait state, the output
of serial output pin, SO₁ can be controlled by setting bit 1 (SM1B1) of serial mode register 1B (SM1B:
$028) to 0 or 1. The output level control example of serial interface 1 is shown in Figure 51. Note that the
output level cannot be controlled in transfer state.
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