H8-3048B Datasheet, PDF (660/901 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcomputer

Section 19 Clock Pulse Generator
External Clock
The external clock frequency should be equal to the system clock frequency (φ) when not divided
by the on-chip frequency divider. Table 19.4, figures 19.6 and 19.7 indicate the clock timing.
When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the
on-chip oscillator and duty adjustment circuit. The resulting stable clock is output to external
devices after the external clock settling time (t_DEXT) has passed after the clock input. The system
must remain reset with the reset signal low during t_DEXT, while the clock output is unstable.
Table 19.4(1) Clock Timing for H8/3048B Group (8 MHz ≤ f ≤ 25 MHz)
V_CC =
3.0 V to 3.6 V
V_CC =
5.0 V ±10%
Item
Symbol Min Max
Min Max
External clock input low t_EXL
pulse width
t_cyc/2–5 —
t_cyc/2–5 —
External clock input high t_EXH
pulse width
t_cyc/2–5 —
t_cyc/2–5 —
External clock rise time t
—
5
EXr
External clock fall time t
—
5
EXf
Clock low pulse width
t_CL
0.4
0.6
Clock high pulse width t_CH
0.4
0.6
External clock output
settling delay time
t_DEXT^*
500
—
—
5
—
5
0.4
0.6
0.4
0.6
500 —
Note:
*
t includes a RES pulse width (t ). t = 20 t
DEXT
RESW RESW
cyc
Test
Unit Conditions
ns Figure 19.6
ns
ns
ns
t_cyc
Figure 21.7
t_cyc
µs Figure 19.7
Rev. 3.00 Sep 27, 2006 page 634 of 872
REJ09B0325-0300