H8-3048B Datasheet, PDF (454/901 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcomputer

Section 11 Programmable Timing Pattern Controller
Bits 5 and 4—Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits
select the compare match event that triggers TPC output group 2 (TP₁₁ to TP₈).
Bit 5: G2CMS1
0
1
Bit 4: G2CMS0
0
1
0
1
Description
TPC output group 2 (TP₁₁ to TP₈) is triggered by compare
match in ITU channel 0
TPC output group 2 (TP₁₁ to TP₈) is triggered by compare
match in ITU channel 1
TPC output group 2 (TP₁₁ to TP₈) is triggered by compare
match in ITU channel 2
TPC output group 2 (TP₁₁ to TP₈) is triggered by compare
match in ITU channel 3
(Initial value)
Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits
select the compare match event that triggers TPC output group 1 (TP₇ to TP₄).
Bit 3: G1CMS1
0
1
Bit 2: G1CMS0
0
1
0
1
Description
TPC output group 1 (TP₇ to TP₄) is triggered by compare
match in ITU channel 0
TPC output group 1 (TP to TP ) is triggered by compare
7
4
match in ITU channel 1
TPC output group 1 (TP₇ to TP₄) is triggered by compare
match in ITU channel 2
TPC output group 1 (TP₇ to TP₄) is triggered by compare
match in ITU channel 3
(Initial value)
Bits 1 and 0—Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits
select the compare match event that triggers TPC output group 0 (TP₃ to TP₀).
Bit 1: G0CMS1
0
1
Bit 0: G0CMS0
0
1
0
1
Description
TPC output group 0 (TP₃ to TP₀) is triggered by compare
match in ITU channel 0
TPC output group 0 (TP₃ to TP₀) is triggered by compare
match in ITU channel 1
TPC output group 0 (TP₃ to TP₀) is triggered by compare
match in ITU channel 2
TPC output group 0 (TP₃ to TP₀) is triggered by compare
match in ITU channel 3
(Initial value)
Rev. 3.00 Sep 27, 2006 page 428 of 872
REJ09B0325-0300