H8-3048B Datasheet, PDF (428/901 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcomputer

Section 10 16-Bit Integrated Timer Unit (ITU)
Contention between TCNT Byte Write and Increment
If an increment pulse occurs in the T₂ or T₃ state of a TCNT byte write cycle, writing takes priority
and TCNT is not incremented. The TCNT byte that was not written retains its previous value. See
figure 10.63, which shows an increment pulse occurring in the T₂ state of a byte write to TCNTH.
TCNTH byte write cycle
T₁
T₂
T₃
φ
Address bus
TCNTH address
Internal write signal
TCNT input clock
TCNTH
TCNTL
N
M
TCNT write data
X
X+1
X
Figure 10.63 Contention between TCNT Byte Write and Increment
Rev. 3.00 Sep 27, 2006 page 402 of 872
REJ09B0325-0300