3826OTP Datasheet, PDF (66/91 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

3826 Group (One Time PROM version)
TIMING REQUIREMENTS
Table 24 Timing requirements 1
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
Parameter
tw(RESET) Reset input “L” pulse width
tc(XIN)
Main clock input cycle time (XIN input)
twH(XIN)
Main clock input “H” pulse width
twL(XIN)
Main clock input “L” pulse width
tc(CNTR)
CNTR0, CNTR1 input cycle time
twH(CNTR) CNTR0, CNTR1 input “H” pulse width
twL(CNTR) CNTR0, CNTR1 input “L” pulse width
twH(INT)
INT0 to INT2 input “H” pulse width
twL(INT)
INT0 to INT2 input “L” pulse width
tc(SCLK1)
Serial I/O1 clock input cycle time (Note)
twH(SCLK1) Serial I/O1 clock input “H” pulse width (Note)
twL(SCLK1) Serial I/O1 clock input “L” pulse width (Note)
tsu(RXD–SCLK1) Serial I/O1 input set up time
th(SCLK1–RXD) Serial I/O1 input hold time
tc(SCLK2)
Serial I/O2 clock input cycle time (Note)
twH(SCLK2) Serial I/O2 clock input “H” pulse width (Note)
twL(SCLK2) Serial I/O2 clock input “L” pulse width (Note)
tsu(SIN2–SCLK2) Serial I/O2 input set up time
th(SCLK2–SIN2) Serial I/O2 input hold time
Note: When bit 6 of address 001A16 is “1”.
Divide this value by four when bit 6 of address 001A16 is “0”.
Table 25 Timing requirements 2
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
Parameter
tw(RESET) Reset input “L” pulse width
tc(XIN)
Main clock input cycle time (XIN input)
twH(XIN)
Main clock input “H” pulse width
twL(XIN)
Main clock input “L” pulse width
tc(CNTR)
CNTR0, CNTR1 input cycle time
twH(CNTR) CNTR0, CNTR1 input “H” pulse width
twL(CNTR) CNTR0, CNTR1 input “L” pulse width
twH(INT)
INT0 to INT2 input “H” pulse width
twL(INT)
INT0 to INT2 input “L” pulse width
tc(SCLK1)
Serial I/O1 clock input cycle time (Note)
twH(SCLK1)
twL(SCLK1)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
tsu(RXD–SCLK1) Serial I/O1 input set up time
th(SCLK1–RXD) Serial I/O1 input hold time
tc(SCLK2)
Serial I/O2 clock input cycle time (Note)
twH(SCLK2) Serial I/O2 clock input “H” pulse width (Note)
twL(SCLK2) Serial I/O2 clock input “L” pulse width (Note)
tsu(SIN2–SCLK2) Serial I/O2 input set up time
th(SCLK2–SIN2) Serial I/O2 input hold time
Note: When bit 6 of address 001A16 is “1”.
Divide this value by four when bit 6 of address 001A16 is “0”.
Limits
Unit
Min. Typ. Max.
2
µs
125
ns
45
ns
40
ns
250
ns
105
ns
105
ns
80
ns
80
ns
800
ns
370
ns
370
ns
220
ns
100
ns
1000
ns
400
ns
400
ns
200
ns
200
ns
Limits
Min.
Typ.
2
125
45
40
500/(VCC-2)
250/(VCC-2)–20
250/(VCC-2)–20
230
230
2000
950
950
400
200
2000
950
950
400
300
Unit
Max.
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev.1.00 Sep 06, 2006 page 66 of 88
REJ03B0181-0100