3826OTP Datasheet, PDF (22/91 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

3826 Group (One Time PROM version)
INTERRUPTS
Interrupts occur by seventeen sources: seven external, nine inter-
nal, and one software. When an interrupt request is accepted, the
program branches to the interrupt jump destination address set in
the vector address (see Table 8).
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt is accepted if the
corresponding interrupt request and enable bits are “1” and the in-
terrupt disable flag is “0”.
Interrupt enable bits can be set to “0” or “1” by program.
Interrupt request bits can be set to “0” by program, but cannot be
set to “1” by program.
The BRK instruction interrupt and reset cannot be disabled with
any flag or bit. When the interrupt disable (I) flag is set to “1”, all
interrupt requests except the BRK instruction interrupt and reset
are not accepted.
When several interrupt requests occur at the same time, the inter-
rupts are received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
matically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt jump destination address is read from the vector
table into the program counter.
3. The interrupt disable flag is set to “1” and the corresponding in-
terrupt request bit is set to “0”.
Table 8 Interrupt vector addresses and priority
Interrupt Source Priority
Vector Addresses (Note 1)
High
Low
Reset (Note 2)
1
INT0
2
FFFD16
FFFB16
FFFC16
FFFA16
INT1
Serial I/O1
reception
Serial I/O1
transmission
Timer X
Timer Y
Timer 2
Timer 3
CNTR0
3
FFF916
4
FFF716
5
FFF516
6
FFF316
7
FFF116
8
FFEF16
9
FFED16
10
FFEB16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
CNTR1
11
FFE916
FFE816
Timer 1
INT2
12
FFE716
13
FFE516
FFE616
FFE416
Serial I/O2
14
FFE316
FFE216
Key input
15
(Key-on wake-up)
ADT
16
FFE116
FFDF16
FFE016
FFDE16
A/D conversion
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of INT1 input
At completion of serial I/O1 data
reception
At completion of serial I/O1
transmit shift or when transmis-
sion buffer is empty
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At timer 1 underflow
At detection of either rising or
falling edge of INT2 input
At completion of serial I/O2 data
transmission or reception
At falling of conjunction of input
level for port P2 (at input mode)
At falling edge of ADT input
At completion of A/D conversion
Remarks
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O2 is selected
External interrupt
(valid at falling)
Valid when ADT interrupt is selected
External interrupt
(valid at falling)
Valid when A/D interrupt is selected
BRK instruction
17
FFDD16
FFDC16
At BRK instruction execution
Notes1: Vector addresses contain interrupt jump destination addresses.
2: Reset is not an interrupt. Reset has the higher priority than all interrupts.
Non-maskable software interrupt
Rev.1.00 Sep 06, 2006 page 22 of 88
REJ03B0181-0100