R1EV58064BXXN Datasheet, PDF (6/25 Pages) Renesas Technology Corp – 64K EEPROM (8-Kword × 8-bit)

R1EV58064BxxN Series/R1EV58064BxxR Series
AC Characteristics
Test Conditions
Ta = 40 to +85C, V_CC = 2.7 to 5.5 V
 Input pulse levels : 0.4 V to 2.4 V (V_CC = 2.7 to 3.6 V), 0.4 V to 3.0 V (V_CC = 3.6 to 5.5 V)
0 V to V_CC (RES pin*²)
 Input rise and fall time :  5 ns
 Input timing reference levels : 0.8, 1.8 V
 Output load : 1TTL Gate +100 pF
 Output reference levels : 1.5 V, 1.5 V
Read Cycle 1 (2.7  V_CC  4.5 V)
Parameter
Symbol
Min
Address to output delay
CE to output delay
OE to output delay
t_ACC

t_CE

t_OE
10
Address to output hold
t_OH
0
OE (CE) high to output float*¹
t_DF
0
RES low to output float*^{1, 2}
t_DFR
0
RES to output delay*²
t_RR
0
Max
100
100
50

40
350
450
Unit
ns
ns
ns
ns
ns
ns
ns
Test conditions
CE = OE = V_IL, WE = V_IH
OE = V_IL, WE = V_IH
CE = V_IL, WE = V_IH
CE = OE = V_IL, WE = V_IH
CE = V_IL, WE = V_IH
CE = OE = V_IL, WE = V_IH
CE = OE= V_IL, WE = V_IH
Write Cycle 1 (2.7  V_CC  4.5 V)
Parameter
Symbol Min*³ Typ Max Unit Test conditions
Address setup time
t_AS
0

 ns
Address hold time
CE to write setup time (WE controlled)
CE hold time (WE controlled)
WE to write setup time (CE controlled)
WE hold time (CE controlled)
OE to write setup time
OE hold time
t_AH
50

 ns
t_CS
0

 ns
t_CH
0

 ns
t_WS
0

 ns
t_WH
0

 ns
t_OES
0

 ns
t_OEH
0

 ns
Data setup time
t_DS
50

 ns
Data hold time
WE pulse width (WE controlled)
CE pulse width (CE controlled)
t_DH
0

t_WP
0.200 
t_CW
0.200 
 ns
30 s
30 s
Data latch time
t_DL
100

 ns
Byte load cycle
t_BLC
0.3

30 s
Byte load window
Write cycle time
t_BL
100

 s
t_WC


10*⁴ ms
Time to device busy
Write start time
Reset protect time*²
Reset high time*^{2, 6}
t_DB
120

 ns
t_DW
0*⁵

 ns
t_RP
100

 s
t_RES
1

 s
Notes: 1. t_DF and t_DFR are defined as the time at which the outputs achieve the open circuit conditions and
are no longer driven.
2. This function is supported by only the R1EV58064BxxR series.
3. Use this device in longer cycle than this value.
4. t_WC must be longer than this value unless polling techniques or RDY/Busy are used. This device automatically
completes the internal write operation within this value.
5. Next read or write operation can be initiated after t_DW if polling techniques or RDY/Busy are used.
6. This parameter is sampled and not 100% tested.
7. A6 through A12 are page addresses and these addresses are latched at the first falling edge of WE.
8. A6 through A12 are page addresses and these addresses are latched at the first falling edge of CE.
9. See AC read characteristics.
R10DS0207EJ0200 Rev.2.00
May 12, 2016
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