PD16715A_15 Datasheet, PDF (6/18 Pages) Renesas Technology Corp – 384-OUTPUT TFT-LCD SOURCE DRIVER(COMPATIBLE WITH 64-GRAY SCALES)

µ PD16715A
4. PIN FUNCTIONS
Pin Symbol
S1 to S384
D00 to D05
D10 to D15
D20 to D25
D30 to D35
D40 to D45
D50 to D55
R,/L
Pin Name
Driver output
Display data input
Shift direction control
input
STHR
STHL
CLK
Right shift start pulse
input/output
Left shift start pulse
input/output
Shift clock input
STB
POL
Latch input
Polarity input
POL2
LPC
Data inversion
Driver voltage selection
V0 to V9
TEST
VDD1
VDD2
VSS1
VSS2
γ -corrected power
supplies
Test pin
Logic power supply
Driver power supply
Logic ground
Driver ground
Description
(1/2)
The D/A converted 64-gray scale analog voltage is output.
The display data is input with a width of 36 bits, viz., the gray scale data (6 bits)
by 6 dots (2 pixels).
DX0 : LSB, DX5: MSB
These refer to the start pulse input/output pins when driver ICs are connected in
cascade. The shift directions of the shift registers are as follows.
R,/L = H: STHR input, S1 → S384, STHL output
R,/L = L : STHL input, S384 → S1, STHR output
R,/L = H: Becomes the start pulse input pin.
R,/L = L : Becomes the start pulse output pin.
R,/L = H: Becomes the start pulse output pin.
R,/L = L : Becomes the start pulse input pin.
Refers to the shift register’s shift clock input. The display data is incorporated into
the data register at the rising edge. At the rising edge of the 64th clock after the
start pulse input, the start pulse output reaches the high level, thus becoming the
start pulse of the next-level driver. The initial-level driver’s 64th clock becomes
valid as the next-level driver’s start pulse is input. If 66 clock pulses are input after
input of the start pulse, input of display data is halted automatically. The contents
of the shift register are cleared at the STB’s rising edge.
The contents of the data register are transferred to the latch circuit at the rising
edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It is
necessary to ensure input of one pulse per horizontal period.
POL = L: The S2n–1 output uses V0 to V4 as the reference supply ;
The S2n output uses V5 to V9 as the reference supply.
POL = H : The S2n–1 output uses V5 to V9 as the reference supply ;
The S2n output uses V0 to V4 as the reference supply.
S2n-1 indicates the odd output: and S2n indicates the even output. Input of the POL
signal is allowed the setup time (tPOL-STB) with respect to STB’s rising edge.
POL2 = H : Display data is inverted.
POL2 = L : Display data is not inverted
The output buffer constant current source is blocked, reducing current consumption.
Low power mode (LPC = ‘H’: DC-level input possible). The condition that low power
mode can be used is that the load constant is at least 10 kΩ + 50 pF.
Input the γ -corrected power supplies from outside by using operational amplifier.
Make sure to maintain the following relationships. During the gray scale voltage
output, be sure to keep the gray scale level power supply at a constant level.
VDD2 – 0.1 V > V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > V8 > V9 > VSS2 + 0.1 V
Test pin. Please input H or Open.
3.3 V ± 0.3 V
11.0 V
+ 2.5
− 2.0
V
Grounding
Grounding
4
Data Sheet S13944EJ2V0DS00