HD74LS195A Datasheet, PDF(6/8 Page) Hitachi Semiconductor – 4-bit Parallel-Access Shift Registers

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HD74LS195A Datasheet, PDF (6/8 Pages) Hitachi Semiconductor – 4-bit Parallel-Access Shift Registers

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HD74LS195A

Waveform

Notes:

Clear

Clock

tTHL

tw (CLR)

tTLH

90%

1.3V

tTLH

90%

10%

1.3V

10%

tsu

tTHL

90% 90%

1.3V

10%

tw (CK)

tsu

tn+1

1.3V

tn+1

1.3V

tsu

Data

1.3V

tsu

trelease

1.3V 1.3V

tsu

trelease

Shift/Load

1.3V 1.3V

tPHL

tPLH

tPHL

Outputs Q

1.3V

VOH

VOL

1. Input pulse; tTLH â¤ 15 ns, tTHL â¤ 6 ns, PRR = 1 MHz, duty cycle 50%

2. A clear pulse is applied prior to each test.

3. Propagation delay times (tPLH and tPHL) are measured at tn + 1. Proper shifting of data is verified

at tn + 4 with a functional test.

4. J and K inputs are tested the same as data A, B, C, and D inputs except that shift / load input

remains high.

5. tn; bit time beroer clocking transition.

6. tn + 1; bit time after one clocking transition.

7. tn + 4; bit time after four clocking transition.

Rev.3.00, Jul.15.2005, page 6 of 7

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