HD74LS195A Datasheet, PDF (2/8 Pages) Hitachi Semiconductor – 4-bit Parallel-Access Shift Registers

HD74LS195A
Function Table
Inputs
Outputs
Clear ^{Shift /} Clock
Load
Serial
J
K
A
Parallel
B
C
D
Q_A
Q_B
Q_C
Q_D
Q_D
L
X
X
X
X
X
X
X
X
L
L
L
L
H
H
L
↑
X
X
a
b
c
d
a
b
c
d
d
H
H
L
X
X
X
X
X
X
Q_A0
Q_B0
Q_C0
Q_D0
Q_D0
H
H
↑
L
H
X
X
X
X
Q_A0
Q_A0
Q_Bn
Q_Cn
Q_Cn
H
H
↑
L
L
X
X
X
X
L
Q_An
Q_Bn
Q_Cn
Q_Cn
H
H
↑
H
H
X
X
X
X
H
Q_An
Q_Bn
Q_Cn
Q_Cn
H
H
↑
H
L
X
X
X
X
Q_An
Q_An
Q_Bn
Q_Cn
Q_Cn
Notes: 1. H; high level, L; low level, X; irrelevant
2. ↑; transition from low to high level
3. a to d; the level of steady-state input at inputs A, B, C, or D, respectively
4. Q_A0 to Q_D0; the level of Q_A, Q_B, Q_C, or Q_D, respectively before the indicated steady-state input conditions were
established.
5. Q_An to Q_Cn; the level of Q_A, Q_B, Q_C, respectively before the most-recent ↑ transition of the clock.
Block Diagram
Shift/Load
Control
Serial
Inputs
Parallel Inputs
JK A
B
C
D
Clock
Clear
Clear
R QA
CK
S QA
Clear
R
CK
S QB
Clear
R
CK
S QC
Clear
R QD
CK
S QD
QA
QB
QC
QD QD
parallel Outputs
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Supply voltage
V_CC
7
V
Input voltage
V_IN
7
V
Power dissipation
P_T
400
mW
Storage temperature
Tstg
–65 to +150
°C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Rev.3.00, Jul.15.2005, page 2 of 7