HD74LS195A Datasheet, PDF (1/8 Pages) Hitachi Semiconductor – 4-bit Parallel-Access Shift Registers

HD74LS195A
4-bit Parallel-Access Shift Register
REJ03D0457–0300
Rev.3.00
Jul.15.2005
This 4-bit register features parallel inputs, parallel outputs, J-K serial inputs, shift / load control input, and a direct
overriding clear. All inputs are buffered to lower the input drive requirements. The registers have two modes of
operation:
• Parallel (broadside) load
• Shift (in the direction Q_A toward Q_D)
Parallel loading is accomplished by applying the four bits of data and taking the shift / load control input low. The data
is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During
loading, serial data flow is inhibited. Shifting is accomplished synchronously when the shift / load control input is high.
Serial data for this mode is entered at the J-K inputs. These inputs permit the first stage to perform as a J-K, D-, or T-
type flip-flop as shown in the function table.
Features
• Ordering Information
Part Name
Package Type
HD74LS195AFPEL SOP-16 pin (JEITA)
Package Code
(Previous Code)
PRSP0016DH-B
(FP-16DAV)
Package
Abbreviation
FP
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
Pin Arrangement
Clear 1
J2
Serial
Inputs _{K 3}
A4
Parallel ^{B 5}
Inputs _{C 6}
D7
GND 8
Clear
J
QA
K
QB
A
QC
B
QD
C
QD
D
CK
Shift/Load
16 V_CC
15 QA
14 QB
13 _QC Outputs
12 QD
11 _QD
10 _Clock
9 _Shift/Load
(Top view)
Rev.3.00, Jul.15.2005, page 1 of 7