HD74HC195 Datasheet, PDF (6/8 Pages) Hitachi Semiconductor – 4-bit Parallel-Access Shift Register

HD74HC195
Test Circuit
VCC
Input
Pulse Generator
Zout = 50 Ω
VCC
Clear
Clock _{QA to QD}
S0
S1
R
L
QD
A to D
Output
Output
C_L = 50 pF
C_L = 50 pF
Note : 1. C_L includes probe and jig capacitance.
Waveforms
• Waveform
tf
tr
tw
Clear
90%
50%
90%
50%
10%
trem
tr
tf
tn
Clock
90%
50%
10%
90%
50%
10%
tw
tsu
tn+1
50%
th
tn ^tn+1
50%
tsu th
V_CC
0V
V_CC
0V
Data
Shift / Load
Q
50%
tsu
trem
50%
50%
50%
50%
tsu
trem
50%
50%
50%
tPHL
90%
50%
10%
tTHL
tPLH
90%
50%
tTLH
tPHL
90%
50%
10%
tTHL
V_CC
0V
V_CC
0V
VOH
VOL
Notes : 1. Input pulse : PRR ≤ 1 MHz, Zo = 50 Ω, t_r ≤ 6 ns, t_f ≤ 6 ns
2. A clear pulse is applied prior to each test.
3. Propagation delay times (tPLH and tPHL ) are measured at tn+1.
Proper shifting of data is verified at tn+4 with a functional test.
4. J and K inputs are tested the same as data A, B, C and D inputs except that
Shift / Load input remains high.
5. tn : bit time before clocking transition.
6. tn+1 : bit time after one clocking transition.
7. tn+4 : bit time after four clocking transition.
Rev.2.00 Jan 31, 2006 page 6 of 7