HD74HC195 Datasheet, PDF (5/8 Pages) Hitachi Semiconductor – 4-bit Parallel-Access Shift Register

HD74HC195
Switching Characteristics
Item
Maximum clock
frequency
Propagation delay
time
Pulse width
Setup time
Hold time
Removal time
Output rise/fall
time
Input capacitance
Symbol V_CC (V)
f_max
2.0
4.5
6.0
t_PHL
2.0
4.5
6.0
t_PLH
2.0
4.5
6.0
t_PHL
2.0
4.5
6.0
t_w
2.0
4.5
6.0
t_su
2.0
4.5
6.0
2.0
4.5
6.0
t_h
2.0
4.5
6.0
t_rem
2.0
4.5
6.0
2.0
4.5
6.0
t_TLH
2.0
t_THL
4.5
6.0
Cin
—
(C_L = 50 pF, Input t_r = t_f = 6 ns)
Ta = 25°C
Ta = –40 to +85°C
Unit
Min Typ Max Min Max
Test Conditions
—— 6
—
5
MH_Z
— — 30
—
24
— — 35
—
28
— — 140 —
175 ns Clock to Q
— 13 28
—
35
— — 24
—
30
— — 140 —
175 ns
— 13 28
—
35
— — 24
—
30
— — 150 —
190 ns Clear to Q
— 15 30
—
38
— — 26
—
33
80 — — 100
—
ns Clock to Clear
16 7 —
20
—
14 — —
17
—
100 — — 125
—
ns A, B, C, D, J, K to Clock
20 6 —
25
—
17 — —
21
—
100 — — 125
—
ns Shift/Load to Clock
20 13 —
25
—
17 — —
21
—
0 ——
0
—
ns Any input except Shift/Load
0 –3 —
0
—
0 ——
0
—
75 — —
95
—
ns Shift/Load to Clock
15 8 —
19
—
13 — —
16
—
25 — —
31
—
ns Clear inactive to Clock
5
0—
6
—
4 ——
5
—
— — 75
—
95
ns
— 5 15
—
19
— — 13
—
16
— 5 10
—
10 pF
Rev.2.00 Jan 31, 2006 page 5 of 7