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HD74HC195 Datasheet, PDF (1/8 Pages) Hitachi Semiconductor – 4-bit Parallel-Access Shift Register
HD74HC195
4-bit Parallel-Access Shift Register
REJ03D0590–0200
(Previous ADE-205-467)
Rev.2.00
Jan 31, 2006
Description
This shift register features parallel inputs, parallel outputs, J-K serial inputs, Shift/Load control input, and a direct
overriding clear. This shift register can operate in two modes: Parallel load; shift from QA towards QD.
Parallel loading is accomplished by applying the four bits of data, and taking the Shift/Load control Input low. The data
is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock input. During
parallel loading, serial data flow is inhibited. Serial shifting occurs synchronously when the Shift/Load control input is
high. Serial data for this mode is entered at the J-K inputs. These inputs allow the first stage to perform as a J-K or
toggle flip-flop as shown in the function table.
Features
• High Speed Operation: tpd (Clock to Q) = 13 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HC195P
DILP-16 pin
PRDP0016AE-B
(DP-16FV)
P
Taping Abbreviation
(Quantity)
—
Function Table
Clear
L
Shift/
Load
X
Clock
X
Inputs
Serial
J
K
A
X
X
X
Parallel
B
C
X
X
Outputs
D
QA
QB
QC
QD
QD
X
L
L
L
L
H
H
L
X
X
a
b
c
d
a
b
c
d
d
H
H
L
X
X
X
X
X
X
QA0
QB0
QC0
QD0
QD0
H
H
L
H
X
X
X
X
QA0
QA0
QBn
QCn
QCn
H
H
L
L
X
X
X
X
L
QAn
QBn
QCn
QCn
H
H
H
H
X
X
X
X
H
QAn
QBn
QCn
QCn
H
H
H
L
X
X
X
X
QAn
QAn
QBn
QCn
QCn
H : high level (steady state)
L : low level (steady state)
X : don’t care
: transition from low to high level.
a, b, c, d : the level of steady-state input at inputs A, B, C or D respectively.
QA0, QB0, QC0, QD0 : the level of QA, QB, QC or QD respectively, before the indicated steady-state input conditions were
established.
QAn, QBn, QCn, QDn : the level of QA, QB, QC or QD respectively before the most recent transition of the clock.
Rev.2.00 Jan 31, 2006 page 1 of 7
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