HD74HC125 Datasheet, PDF (6/9 Pages) Hitachi Semiconductor – Quad. Bus Buffer Gates (with 3-state outputs)

HD74HC125/HD74HC126
Waveforms
• HD74HC126
• Waveform – 1
tr
tf
90 %
90 %
V_CC
Input A
50 %
50 %
10 %
10 %
0V
t_PLH
t_PHL
Output Y
50 %
V_OH
50 %
V_OL
• Waveform – 2
tr
tf
90 %
90 %
V_CC
Input C
50 %
50 %
10 %
10 %
0V
t_ZL
t_LZ
Waveform - A
50 %
t_ZH
10 %
t_HZ
V_OH
V_OL
Waveform - B
50 %
90 %
V_OH
V_OL
Notes : 1. t_r ≤ 6 ns, t_f ≤ 6 ns
2. Input waveform : PRR ≤ 1 MHz, duty cycle 50%
3. Waveform– A is for an output with internal conditions such that the
output is low except when disabled by the output control.
4. Waveform– B is for an output with internal conditions such that the
output is high except when disabled by the output control.
Rev.2.00, Oct 11, 2005 page 6 of 8