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HD74HC125 Datasheet, PDF (5/9 Pages) Hitachi Semiconductor – Quad. Bus Buffer Gates (with 3-state outputs) | |||
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HD74HC125/HD74HC126
Waveforms
⢠HD74HC125
⢠Waveform â 1
tr
tf
90 %
90 %
VCC
Input A
50 %
50 %
10 %
10 %
0V
tPLH
tPHL
Output Y
50 %
VOH
50 %
VOL
⢠Waveform â 2
tf
tr
Input C
90 %
50 %
90 %
VCC
50 %
10 %
10 %
0V
tZL
tLZ
Waveform - A
50 %
tZH
10 %
tHZ
VOH
VOL
Waveform - B
50 %
90 %
VOH
VOL
Notes : 1. tr ⤠6 ns, tf ⤠6 ns
2. Input waveform : PRR ⤠1 MHz, duty cycle 50%
3. Waveformâ A is for an output with internal conditions such that the
output is low except when disabled by the output control.
4. Waveformâ B is for an output with internal conditions such that the
output is high except when disabled by the output control.
Rev.2.00, Oct 11, 2005 page 5 of 8
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