R8A66597FP Datasheet, PDF (59/185 Pages) Renesas Technology Corp – ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)

R8A66597FP/DFP/BG
♦ Interrupt status register 2 [INTSTS2]
<Address: 44H>
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
OVRCR BCHG
DTCH ATTCH
EOFERR
0
0
?
0
0
?
?
?
?
0
?
?
?
?
?
?
-
-
?
-
-
?
?
?
?
-
?
?
?
?
?
?
Bit
Name
Function
Software Hardware Remarks
15
OVRCR
Port1 OVRCR interrupt status
Port1 OVRCR interrupt status is set. When the input
status of the OVCUR1 pin is modified, this interrupt is
issued.
R/W(0)
0: OVRCR interrupt not issued
1: OVRCR interrupt issued
BCHG
Port1 USB bus modify interrupt status is set.
14 Port1 USB bus modify interrupt 0: BCHGinterrupt not issued
status
1: BCHGinterrupt issued
R/W(0)
H
(Read
W
value
invalid
when P)
H
(Read
W
value
invalid
when P)
13 Unassigned. Fix to "0".
DTCH
Port1 detach detect interrupt status is set.
12 Port1 detach detect interrupt 0: DTCHinterrupt not issued
status
1: DTCHinterrupt issued
ATTCH
Port1 ATTCH interrupt status is set.
11 Port1 attach detect interrupt 0: ATTCH interrupt not issued
status
1: ATTCH interrupt issued
R/W(0)
R/W(0)
H
(Read
W
value
invalid
when P)
H
(Read
W
value
invalid
when P)
10-7 Unassigned. Fix to "0".
EOFERR
Port1 EOFERR interrupt status is set.
6 Port1 EOF error detect interrupt 0: EOFERR interrupt not issued
status
1: EOFERR interrupt issued
5-0 Unassigned. Fix to "0".
R/W(0)
H
(Read
R
value
invalid
when P)
Remarks
* Enable the interrupt caused by the changes in status shown by each bit of the register, only when the Host Controller function
is selected.
* To clear the status of each bit of this register, use the software to write "0" only to the bit which is to be cleared, and "1" to the
other bits.
* The controller detects the change in status indicated by the OVRCR and BCHG bits of this register, even while the clock is
being stopped ("SCKE=0"), and notifies the interrupt if the corresponding interrupt is enabled. When the clock is enabled, use
the software to clear the status. Interrupt for the bits other than the OVRCR and BCHG bits cannot be detected while the clock
is being stopped ("SCKE=0").
Rev1.01 Oct 17, 2008 page 59 of 183