R8A66597FP Datasheet, PDF (50/185 Pages) Renesas Technology Corp – ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)

R8A66597FP/DFP/BG
♦ BRDY interrupt enabled register [BRDYENB]
<Address: 36H>
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PIPEBRDYE
?
?
?
?
?
?
0
0
0
0
0
0
0
0
0
0
?
?
?
?
?
?
-
-
-
-
-
-
-
-
-
-
Bit
Name
Function
Software Hardware Remarks
15-10 Unassigned. Fix to "0".
PIPEBRDYE
9-0 Interrupts for
enabled
each
pipe
Specify whether it is possible to write "1" to the
are
BRDY bit while detecting the
0: Interrupt output disabled
BRDY
bit
of
each
pipe.
1: Interrupt output enabled
R/W
R
Remarks
* The bit number corresponds to the pipe number.
2.9.2
BRDY interrupt enabled bit of each pipe (PIPEBRDYE)
When the controller detects the BRDY interrupt for the pipe for which the software has written "1" in this bit, it sets "1"
to the BRDYSTS register PIPEBRDY bit and to the INTSTS0 register BRDY bit, and asserts an interrupt from the
INT_N pin.
When at least one bit from the BRDYSTS register PIPEBRDY bit sets "1", if the software modifies the register interrupt
enabled bit from "0" to "1", the controller asserts an interrupt from the INT_N pin.
♦ NRDY interrupt enabled register [NRDYENB]
<Address: 38H>
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PIPENRDYE
?
?
?
?
?
?
0
0
0
0
0
0
0
0
0
0
?
?
?
?
?
?
-
-
-
-
-
-
-
-
-
-
Bit
Name
Function
Software Hardware Remarks
15-10 Unassigned. Fix to "0".
9-0
PIPENRDYE
NRDY interrupt for each pipe
enabled
is
Specify whether it is possible to write "1" to the NRDY
bit while detecting the BRDY interrupt of each pipe.
0: Interrupt output disabled
1: Interrupt output enabled
R/W
R
Remarks
* Bit number corresponds to the pipe number.
2.9.3
NRDY interrupt enabled bit of each pipe (PIPENRDYE)
When the controller detects the NRDY interrupt for the pipe for which the software has written "1" to this bit, it sets "1"
to the NRDYSTS register PIPEBRDY bit and to the INTSTS0 register NRDY bit, and asserts an interrupt from the
INT_N pin.
When at least one bit from the NRDYSTS register PIPENRDY bit sets "1", if the software modifies the interrupt enabled
bit of the register from "0" to "1", the controller asserts an interrupt from the INT_N pin.
Rev1.01 Oct 17, 2008 page 50 of 183