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HD64F3694FP Datasheet, PDF (58/452 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
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Section 2 CPU
Table 2.4 Logic Operations Instructions
Instruction Size* Function
AND
B/W/L
Rd ⧠Rs â Rd, Rd ⧠#IMM â Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR
B/W/L Rd ⨠Rs â Rd, Rd ⨠#IMM â Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR
B/W/L
Rd â Rs â Rd, Rd â #IMM â Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT
B/W/L
¬ (Rd) â (Rd)
Takes the one's complement (logical complement) of general register
contents.
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2.5 Shift Instructions
Instruction Size* Function
SHAL
SHAR
B/W/L Rd (shift) â Rd
Performs an arithmetic shift on general register contents.
SHLL
SHLR
B/W/L Rd (shift) â Rd
Performs a logical shift on general register contents.
ROTL
ROTR
B/W/L Rd (rotate) â Rd
Rotates general register contents.
ROTXL
ROTXR
B/W/L Rd (rotate) â Rd
Rotates general register contents through the carry flag.
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
Rev.5.00 Nov. 02, 2005 Page 28 of 418
REJ09B0028-0500
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