H8S2153 Datasheet, PDF (573/750 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 19 Flash Memory
(b) Flash pass/fail parameter (FPFR: general register R0L of CPU)
This parameter returns value of the erasing processing result.
Initial
Bit
Bit Name Value R/W Description
7



Unused
Return 0.
6
MD

R/W Programming Mode Related Setting Error Detect
Returns the check result that a high level signal is input
to the FWE pin and the error protection state is not
entered. When the low level signal is input to the FWE
pin or the error protection state is entered, 1 is written to
this bit. The state can be confirmed with the FWE and
FLER bits in FCCS. For conditions to enter the error
protection state, see section 19.5.3, Error Protection.
0: FWE and FLER settings are normal (FWE = 1,
FLER = 0)
5
EE

1: Programming cannot be performed (FWE = 0 or
FLER = 1)
R/W Erasure Execution Error Detect
1 is returned to this bit when the user MAT could not be
erased or when flash-memory related register settings
are partially changed. If this bit is set to 1, there is a high
possibility that the user MAT is partially erased. In this
case, after removing the error factor, erase the user
MAT. If FMATS is set to H'AA and the user boot MAT is
selected, an error occurs when erasure is performed. In
this case, both the user MAT and user boot MAT are not
erased. Erasing of the user boot MAT should be
performed in boot mode or programmer mode.
0: Erasure has ended normally
4
FK

1: Erasure has ended abnormally (erasure result is not
guaranteed)
R/W Flash Key Register Error Detect
Returns the check result of FKEY value before start of
the erasing processing.
0: FKEY setting is normal (FKEY = H'5A)
1: FKEY setting is error (FKEY = value other than H'5A)
Rev. 2.00 Sep.11, 2008 Page 537 of 710
REJ09B0384-0200