H8S2153 Datasheet, PDF (276/750 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 12 Watchdog Timer (WDT)
• TCSR_1
Bit Bit Name
7
OVF
6
WT/IT
5
TME
4
PSS
3
RST/NMI
Initial
Value
0
0
0
0
0
R/W Description
R/(W)*¹ Overflow Flag
Indicates that TCNT has overflowed (changes from H'FF
to H'00).
[Setting conditions]
• When TCNT overflows (changes from H'FF to H'00)
• When internal reset request generation is selected in
watchdog timer mode, OVF is cleared automatically by
the internal reset.
[Clearing conditions]
• When TCSR is read when OVF = 1*², then 0 is written
to OVF
• When 0 is written to TME
R/W Timer Mode Select
Selects whether the WDT is used as a watchdog timer or
interval timer.
0: Interval timer mode
1: Watchdog timer mode
R/W Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and is
initialized to H'00.
When the PSS bit is 1, TCNT is not initialized. Write H'00
to initialize TCNT.
R/W Prescaler Select
Selects the clock source to be input to TCNT.
0: Counts the divided cycle of φ–based prescaler (PSM)
1: Counts the divided cycle of φSUB–based prescaler
(PSS)
R/W Reset or NMI
Selects to request an internal reset or an NMI interrupt
when TCNT has overflowed.
0: An NMI interrupt is requested
1: An internal reset is requested
Rev. 2.00 Sep.11, 2008 Page 240 of 710
REJ09B0384-0200