H8S2153 Datasheet, PDF (371/750 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 15 I²C Bus Interface (IIC)
15.3.4 I²C Bus Mode Register (ICMR)
ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit
in ICCR is set to 1.
Initial
Bit Bit Name Value R/W Description
7
MLS
0
R/W MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I²C bus format is used.
6
WAIT
0
R/W Wait Insertion Bit
This bit is valid only in master mode with the I²C bus
format.
0: Data and the acknowledge bit are transferred
consecutively with no wait inserted.
1: After the fall of the clock for the final data bit (8th
clock), the IRIC flag is set to 1 in ICCR, and a wait state
begins (with SCL at the low level). When the IRIC flag
is cleared to 0 in ICCR, the wait ends and the
acknowledge bit is transferred.
For details, refer to section 15.4.7, IRIC Setting Timing
and SCL Control.
5
CKS2
All 0 R/W Transfer Clock Select
4
CKS1
These bits are used only in master mode.
3
CKS0
These bits select the required transfer rate, together with
the IICX3 (channel 3) bit in IICX3, the IICX2 (channel 2),
IICX1 (channel 1), and IICX0 (channel 0) bits in STCR.
Refer to table 15.3.
Rev. 2.00 Sep.11, 2008 Page 335 of 710
REJ09B0384-0200