H8-3006 Datasheet, PDF (545/796 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

15. A/D Converter
data register are reserved bits that are always read as 0. Table 15.3 indicates the pairings of analog
input channels and A/D data registers.
The CPU can always read the A/D data registers. The upper byte can be read directly, but the
lower byte is read through a temporary register (TEMP). For details see section 15.3, CPU
Interface.
The A/D data registers are initialized to H'0000 by a reset and in standby mode.
Table 15.3 Analog Input Channels and A/D Data Registers
Analog Input Channel
Group 0
Group 1
AN₀
AN₁
AN₂
AN₃
AN₄
AN₅
AN₆
AN₇
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
Rev.5.00 Sep. 12, 2007 Page 517 of 764
REJ09B0396-0500