H8-3006 Datasheet, PDF (451/796 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

12. Watchdog Timer
12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST)
The WRST bit in RSTCSR is valid when bits WT/IT and TME are both set to 1 in TCSR.
Figure 12.7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is
set to 1 when TCNT overflows and OVF is set to 1. At the same time an internal reset signal is
generated for the entire H8/3006 and H8/3007 chip. This internal reset signal clears OVF to 0, but
the WRST bit remains set to 1. The reset routine must therefore clear the WRST bit.
φ
TCNT
H'FF
H'00
Overflow signal
OVF
WDT internal
reset
WRST
Figure 12.7 Timing of Setting of WRST Bit and Internal Reset
12.4 Interrupts
During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The
interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR.
Rev.5.00 Sep. 12, 2007 Page 423 of 764
REJ09B0396-0500