H8-3006 Datasheet, PDF (162/796 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

6. Bus Controller
Output
of
CS
4
to
CS₇:
Output
of
CS
4
to
CS
7
is
enabled
or
disabled
in
the
chip
select
control
register (CSCR). A reset leaves pins CS₄ to CS₇ in the input state. To output chip select signals CS₄
to CS₇, the corresponding CSCR bits must be set to 1. For details, see section 8, I/O Ports.
φ
Address bus
External address in area n
CSn
Figure 6.4 CSn Signal Output Timing (n = 0 to 7)
When
the
on-chip
RAM
and
on-chip
registers
are
accessed,
CS
0
to
CS
7
remain
high.
The
CS
n
signals are decoded from the address signals. They can be used as chip select signals for SRAM
and other devices.
6.4 Basic Bus Interface
6.4.1 Overview
The basic bus interface enables direct connection of ROM, SRAM, and so on.
The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL
(see table 6.3).
6.4.2 Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and when accessing external space, controls whether the
upper data bus (D₁₅ to D₈) or lower data bus (D₇ to D₀) is used according to the bus specifications
for the area being accessed (8-bit access area or 16-bit access area) and the data size.
Rev.5.00 Sep. 12, 2007 Page 134 of 764
REJ09B0396-0500