H8S2140B Datasheet, PDF (532/845 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Section 16 I²C Bus Interface (IIC) (Optional)
Table 16.11 I²C Bus Timing (with Maximum Influence of t_Sr/t_Sf)
Item
t_cyc
Indication
Time Indication (at Maximum Transfer Rate) [ns]
I²C Bus
t_Sr/t_Sf
Specifi-
Influence cation φ =
(Max.) (Min.) 5 MHz
φ=
8 MHz
φ=
φ=
φ=
10 MHz 16 MHz 20 MHz
t_SCLHO
0.5 t_SCLO (–t_Sr) Standard mode –1000
High-speed mode –300
4000
600
4000
950
4000
950
4000
950
4000
950
4000
950
t_SCLLO
t_BUFO
0.5 t_SCLO (–t_Sf) Standard mode –250
High-speed mode –250
0.5 t_SCLO –1 t_cyc Standard mode –1000
(–t_Sr)
High-speed mode –300
4700
1300
4700
1300
4750 4750 4750
1000^*1 1000^*1 1000^*1
3800^*1 3875^*1 3900^*1
750^*1 825^*1 850^*1
4750
1000^*1
3938^*1
888^*1
4750
1000^*1
3950^*1
900^*1
t_STAHO
0.5 t_SCLO –1 t_cyc Standard mode –250
(–t_Sf)
High-speed mode –250
4000
600
4550
800
4625
875
4650
900
4688
938
4700
950
t_STASO
1 t_SCLO (–t_Sr)
Standard mode –1000
High-speed mode –300
4700
600
9000
2200
9000
2200
9000
2200
9000
2200
9000
2200
t_STOSO
0.5 t + _SCLO 2 t_cyc Standard mode –1000
(–t_Sr)
High-speed mode –300
t_SDASO
1
t *3
SCLLO
–3
t_cyc
Standard mode
–1000
(master) (–t_Sr)
High-speed mode –300
4000
600
250
100
4400
1350
3100
400
4250
1200
3325
625
4200
1150
3400
700
4125
1075
3513
813
4100
1050
3550
850
t_SDASO
(slave)
1
t *3
SCLL
–12
t *2
cyc
(–t_Sr)
Standard mode –1000 250
1300 2200 2500 2950 3100
High-speed mode –300
100
–1400^*1 –500^*1 –200^*1 250
400
t_SDAHO
3 t_cyc
Standard mode 0
0
600 375 300
188
150
High-speed mode 0
0
600 375 300
188
150
Notes: 1. Does not meet the I²C bus interface specification. Remedial action such as the following
is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and
fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate;
(d) select slave devices whose input timing permits this output timing.
The values in the above table will vary depending on the settings of the IICX bit and bits
CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the
maximum transfer rate; therefore, whether or not the I²C bus interface specifications are
met must be determined in accordance with the actual setting conditions.
2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is
(t_SCLL – 6t_cyc).
3. Calculated using the I²C bus specification values (standard mode: 4700 ns min.; high-
speed mode: 1300 ns min.).
Rev. 3.00 Mar 21, 2006 page 478 of 788
REJ09B0300-0300