H8S2140B Datasheet, PDF (105/845 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Section 2 CPU
(1) Operation field only
op
NOP, RTS
(2) Operation field and register fields
op
rn
rm
ADD.B Rn, Rm
(3) Operation field, register fields, and effective address extension
op
rn
EA (disp)
rm
MOV.B @(d:16, Rn), Rm
(4) Operation field, effective address extension, and condition field
op
cc
EA (disp)
BRA d:16
Figure 2.11 Instruction Formats (Examples)
2.7 Addressing Modes and Effective Address Calculation
The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes.
Arithmetic and logic operations instructions can use the register direct and immediate addressing
modes. Data transfer instructions can use all addressing modes except program-counter relative
and memory indirect. Bit manipulation instructions can use register direct, register indirect, or
absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and
BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.
Rev. 3.00 Mar 21, 2006 page 51 of 788
REJ09B0300-0300