H8S2140B Datasheet, PDF (479/845 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Section 16 I²C Bus Interface (IIC) (Optional)
Bit Bit Name Initial Value R/W Description
5 MST
0
R/W [MST clearing conditions]
4 TRS
0
1. When 0 is written by software
2. When lost in bus contention in I²C bus format master
mode
[MST setting conditions]
1. When 1 is written by software (for MST clearing
condition 1)
2. When 1 is written in MST after reading MST = 0 (for
MST clearing condition 2)
[TRS clearing conditions]
1. When 0 is written by software (except for TRS setting
condition 3)
2. When 0 is written in TRS after reading TRS = 1 (for
TRS setting condition 3)
3 When lost in bus contention in I²C bus format master
mode
4. When the SW bit in DDCSWR is changed from 1 to 0
[TRS setting conditions]
1. When 1 is written by software (except for TRS clearing
conditions 3 and 4)
2. When 1 is written in TRS after reading TRS = 0 (for
TRS clearing conditions 3 and 4)
3. When 1 is received as the R/W bit after the first frame
address matching in I²C bus format slave mode
3 ACKE
0
R/W Acknowledge Bit Decision and Selection
0: The value of the acknowledge bit is ignored, and
continuous transfer is performed. The value of the
received acknowledge bit is not indicated by the ACKB
bit in ICSR, which is always 0.
1: If the received acknowledge bit is 1, continuous
transfer is halted.
Depending on the receiving device, the acknowledge bit
may be significant, in indicating completion of processing
of the received data, for instance, or may be fixed at 1 and
have no significance.
Rev. 3.00 Mar 21, 2006 page 425 of 788
REJ09B0300-0300