R5F52108ADFP Datasheet, PDF(52/92 Page) Renesas Technology Corp – 50-MHz 32-bit RX MCUs, 78 DMIPS, up to 512-KB flash memory, 12-bit AD, 10-bit DA

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

R5F52108ADFP Datasheet, PDF (52/92 Pages) Renesas Technology Corp – 50-MHz 32-bit RX MCUs, 78 DMIPS, up to 512-KB flash memory, 12-bit AD, 10-bit DA

◁

Under development Preliminary document

Specifications in this document are tentative and subject to change.

RX210 Group

2. CPU

Table 2.14 Instructions that are Converted into Multiple Micro-Operations (2 / 2)

Instruction

Mnemonic (indicates the common operation when

the size is omitted)

String manipulation instructions*5 ï· SCMPU

Reference

Figure

ï· SMOVB

ï· SMOVF, SMOVU

ï· SSTR.B

ï· SSTR.W

ï· SSTR.L

ï· SUNTIL.B, SWHILE.B

ï· SUNTIL.W, SWHILE.W

ï· SUNTIL.L, SWHILE.L

System manipulation instructions ï· RTE

ï· RTFI

?: Conditional operator

Number of Cycles

2+4Ãfloor(n/4)+4Ã(n%4)

n: Number of comparison

bytes*1

n>3?

6+3Ãfloor(n/4)+3Ã(n%4):

2+3n

n: Number of transfer

bytes*1

2+3Ãfloor(n/4)+3Ã(n%4)

n: Number of transfer

bytes*1

2+floor(n/4)+n%4

n: Number of transfer

bytes*1

2+floor(n/2)+n%2

n: Number of transfer

words*1

2+n

n: Number of transfer

longwords

3+3Ãfloor(n/4)+3Ã(n%4)

n: Number of comparison

bytes*1

3+3Ãfloor(n/2)+3Ã(n%2)

n: Number of comparison

words*1

3+3Ãn

n: Number of comparison

longwords

Note 1. floor(x): Max. integer that is smaller than x

Note 2. For the number of cycles for throughput and latency, see section 2.8.3, Calculation of the Instruction Processing Time.

Note 3. The PUSHM instruction is converted into multiple store operations. The pipeline processing is the same as the one for the store

operations of the MOV instruction, where the operation is repeated for the number of specified registers.

Note 4. The POPM instruction is converted into multiple load operations. The pipeline processing is the same as the one for the load

operations of the MOV instruction, where the operation is repeated for the number of specified registers.

Note 5. Each of the SCMPU, SMOVU, SWHILE, and SUNTIL instructions ends the execution regardless of the specified cycles, if the

end condition is satisfied during execution.

R01DS0041EJ0050 Rev.0.50

Apr 15, 2011

Page 52 of 90

▷