R5F52108ADFP Datasheet, PDF (33/92 Pages) Renesas Technology Corp – 50-MHz 32-bit RX MCUs, 78 DMIPS, up to 512-KB flash memory, 12-bit AD, 10-bit DA

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RX210 Group
2.2.2.6
Backup PSW (BPSW)
b31
Value after reset: Undefined
2. CPU
b0
The backup PSW (BPSW) is provided to speed up response to interrupts.
After a fast interrupt has been generated, the contents of the processor status word (PSW) are saved in the BPSW. The
allocation of bits in the BPSW corresponds to that in the PSW.
2.2.2.7
Fast Interrupt Vector Register (FINTV)
b31
b0
Value after reset: Undefined
The fast interrupt vector register (FINTV) is provided to speed up response to interrupts.
The FINTV register specifies a branch destination address when a fast interrupt has been generated.
2.2.3
Register Associated with DSP Instructions
2.2.3.1
Accumulator (ACC)
Range for reading by MVFACMI
b63
b48 b47
b32 b31
b16 b15
b0
Value after reset: Undefined
Range for reading and writing by
MVTACHI and MVFACHI
Range for writing by MVTACLO
The accumulator (ACC) is a 64-bit register used for DSP instructions. The accumulator is also used for the multiply and
multiply-and-accumulate instructions; EMUL, EMULU, MUL, and RMPA, in which case the prior value in the
accumulator is modified by execution of the instruction.
Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The MVTACHI and MVTACLO
instructions write data to the higher-order 32 bits (bits 63 to 32) and the lower-order 32 bits (bits 31 to 0), respectively.
Use the MVFACHI and MVFACMI instructions for reading data from the accumulator. The MVFACHI and MVFACMI
instructions read data from the higher-order 32 bits (bits 63 to 32) and the middle 32 bits (bits 47 to 16), respectively.
R01DS0041EJ0050 Rev.0.50
Apr 15, 2011
Page 33 of 90