3804H_M Datasheet, PDF (52/387 Pages) Renesas Technology Corp – 8-BIT CISC SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES

3804 Group (Spec.H)
HARDWARE
FUNCTIONAL DESCRIPTION
(6) Programmable waveform generating mode
qMode selection
This mode can be selected by setting “100” to the timer Z operat-
ing mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z mode register (address
002A16).
qCount source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64,
1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected
as the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/
512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count
source.
qInterrupt
The interrupt at an underflow is the same as the timer mode’s.
qExplanation of operation
The operation is the same as the timer mode’s. Moreover the
timer outputs the data set in the output level latch (bit 4) of the
timer Z mode register (address 002A16) from the CNTR2 pin each
time the timer underflows.
Changing the value of the output level latch and the timer latch af-
ter an underflow makes it possible to output an optional waveform
from the CNTR2 pin.
sPrecautions
The double-function port of CNTR2 pin and port P47 is automati-
cally set to the programmable waveform generating port in this
mode.
Figure 30 shows the timing chart of the programmable waveform
generating mode.
(7) Programmable one-shot generating mode
qMode selection
This mode can be selected by setting “101” to the timer Z operat-
ing mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z mode register (address
002A16).
qCount source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as
the count source.
qInterrupt
The interrupt at an underflow is the same as the timer mode’s.
The trigger to generate one-shot pulse can be selected by the
INT1 active edge selection bit (bit 1) of the interrupt edge selection
register (address 003A16). When it is “0”, the falling edge active is
selected; when it is “1”, the rising edge active is selected.
When the valid edge of the INT1 pin is detected, the INT1 interrupt
request bit (bit 1) of the interrupt request register 1 (address
003C16) is set to “1”.
qExplanation of operation
•“H” one-shot pulse; Bit 5 of timer Z mode register = “0”
The output level of the CNTR2 pin is initialized to “L” at mode se-
lection. When trigger generation (input signal to INT1 pin) is
detected, “H” is output from the CNTR2 pin. When an underflow
occurs, “L” is output. The “H” one-shot pulse width is set by the
setting value to the timer Z register low-order and high-order.
When trigger generating is detected during timer count stop, al-
though “H” is output from the CNTR2 pin, “H” output state
continues because an underflow does not occur.
•“L” one-shot pulse; Bit 5 of timer Z mode register = “1”
The output level of the CNTR2 pin is initialized to “H” at mode se-
lection. When trigger generation (input signal to INT1 pin) is
detected, “L” is output from the CNTR2 pin. When an underflow
occurs, “H” is output. The “L” one-shot pulse width is set by the
setting value to the timer Z low-order and high-order. When trigger
generating is detected during timer count stop, although “L” is out-
put from the CNTR2 pin, “L” output state continues because an
underflow does not occur.
sPrecautions
Set the double-function port of INT1 pin and port P42 to input in
this mode.
Set the double-function port of CNTR2 pin and port P22 is auto-
matically set to the programmable one-shot generating port in this
mode.
This mode cannot be used in low-speed mode.
If the value of the CNTR2 active edge switch bit is changed during
one-shot generating enabled or generating one-shot pulse, then
the output level from CNTR2 pin changes.
Figure 31 shows the timing chart of the programmable one-shot
generating mode.
sNotes regarding all modes
qTimer Z write control
Which write control can be selected by the timer Z write control bit
(bit 3) of the timer Z mode register (address 002A16), writing data
to both the latch and the timer at the same time or writing data
only to the latch.
When the operation “writing data only to the latch” is selected, the
value is set to the timer latch by writing data to the address of
timer Z and the timer is updated at next underflow. After reset re-
lease, the operation “writing data to both the latch and the timer at
the same time” is selected, and the value is set to both the latch
and the timer at the same time by writing data to the address of
timer Z.
In the case of writing data only to the latch, if writing data to the
latch and an underflow are performed almost at the same time,
the timer value may become undefined.
qTimer Z read control
A read-out of timer value is impossible in pulse period measure-
ment mode and pulse width measurement mode. In the other
modes, a read-out of timer value is possible regardless of count
operating or stopped.
However, a read-out of timer latch value is impossible.
qSwitch of interrupt active edge of CNTR2 and INT1
Each interrupt active edge depends on setting of the CNTR2 ac-
tive edge switch bit and the INT1 active edge selection bit.
qSwitch of count source
When switching the count source by the timer Z count source se-
lection bits, the value of timer count is altered in inconsiderable
amount owing to generating of thin pulses on the count input sig-
nals.
Therefore, select the timer count source before setting the value
to the prescaler and the timer.
qUsage of CNTR2 pin as normal I/O port
To use the CNTR2 pin as normal I/O port P47, set timer Z operat-
ing mode bits (b2, b1, b0) of timer Z mode register (address
002A16) to “000”.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-34