H8S2604 Datasheet, PDF (516/574 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 21 List of Registers
21.1 Register Addresses (Address Order)
The data-bus width column indicates the number of bits. The access-state column shows the
number of states of the selected basic clock that is required for access to the register.
Register Name
Number
Data Access
Abbreviation of Bits Address^* Module Width State
SS control register H_0
SSCRH_0 8
H'FB00 SSU_0 16 3
SS control register L_0
SSCRL_0 8
H'FB01 SSU_0 16 3
SS mode register_0
SSMR_0
8
H'FB02 SSU_0 16 3
SS enable register_0
SSER_0
8
H'FB03 SSU_0 16 3
SS status register_0
SSSR_0
8
H'FB04 SSU_0 16 3
SS transmit data register 0_0
SSTDR0_0 8
H'FB06 SSU_0 16 3
SS transmit data register 1_0
SSTDR1_0 8
H'FB07 SSU_0 16 3
SS transmit data register 2_0
SSTDR2_0 8
H'FB08 SSU_0 16 3
SS transmit data register 3_0
SSTDR3_0 8
H'FB09 SSU_0 16 3
SS receive data register 0_0
SSRDR0_0 8
H'FB0A SSU_0 16 3
SS receive data register 1_0
SSRDR1_0 8
H'FB0B SSU_0 16 3
SS receive data register 2_0
SSRDR2_0 8
H'FB0C SSU_0 16 3
SS receive data register 3_0
SSRDR3_0 8
H'FB0D SSU_0 16 3
SS control register H_1
SSCRH_1 8
H'FB10 SSU_1 16 3
SS control register L_1
SSCRL_1 8
H'FB11 SSU_1 16 3
SS mode register_1
SSMR_1
8
H'FB12 SSU_1 16 3
SS enable register_1
SSER_1
8
H'FB13 SSU_1 16 3
SS status register_1
SSSR_1
8
H'FB14 SSU_1 16 3
SS transmit data register 0_1
SSTDR0_1 8
H'FB16 SSU_1 16 3
SS transmit data register 1_1
SSTDR1_1 8
H'FB17 SSU_1 16 3
SS transmit data register 2_1
SSTDR2_1 8
H'FB18 SSU_1 16 3
SS transmit data register 3_1
SSTDR3_1 8
H'FB19 SSU_1 16 3
SS receive data register 0_1
SSRDR0_1 8
H'FB1A SSU_1 16 3
SS receive data register 1_1
SSRDR1_1 8
H'FB1B SSU_1 16 3
SS receive data register 2_1
SSRDR2_1 8
H'FB1C SSU_1 16 3
SS receive data register 3_1
SSRDR3_1 8
H'FB1D SSU_1 16 3
Port D realtime input data register PDRTIDR 8
H'FB40 PORT 16 3
Rev. 1.00 Jan. 24, 2008 Page 480 of 534
REJ09B0426-0100