H8S2604 Datasheet, PDF (337/574 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 13 Watchdog Timer
13.2.2 Timer Control/Status Register (TCSR)
TCSR is an 8-bit readable/writable register. Its functions include selecting the clock source to be
input to TCNT, and selecting the timer mode.
Bit Bit Name
7
OVF
6
WT/IT
5
TME
4, 3 
Initial Value
0
0
0
All 1
R/W
R/(W)^*
R/W
R/W

Description
Overflow Flag
Indicates that TCNT has overflowed. Only a write
of 0 is permitted, to clear the flag.
[Setting condition]
• When TCNT overflows (changes from H'FF to
H'00)
When internal reset request generation is
selected in watchdog timer mode, OVF is
cleared automatically by the internal reset.
[Clearing condition]
• Cleared by reading TCSR when OVF = 1, then
writing 0 to OVF
Timer Mode Select
Selects whether the WDT is used as a watchdog
timer or an interval timer.
0: Interval timer mode
1: Watchdog timer mode
Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and
is initialized to H'00.
Reserved
These bits are always read as 1 and cannot be
modified.
Rev. 1.00 Jan. 24, 2008 Page 301 of 534
REJ09B0426-0100