H8S2604 Datasheet, PDF (491/574 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Bit Bit Name
2
SCK2
1
SCK1
0
SCK0
[Legend]
×: Don’t care
Section 19 Clock Pulse Generator
Initial Value R/W
0
R/W
0
R/W
0
R/W
Description
System Clock Select 2 to 0
These bits select the bus master clock.
000: High-speed mode
001: Medium-speed clock is φ/2
010: Medium-speed clock is φ/4
011: Medium-speed clock is φ/8
100: Medium-speed clock is φ/16
101: Medium-speed clock is φ/32
11×: Setting prohibited
19.1.2 Low-Power Control Register (LPWRCR)
Bit Bit Name
7 to 4 
3, 2 
1
STC1
0
STC0
Initial Value R/W
All 0

All 0
R/W
0
R/W
0
R/W
Description
Reserved
The write value should always be 0.
Reserved
These bits can be read from and write to, but
should not be set to 1.
Frequency Multiplication Factor
The STC bits specify the frequency multiplication
factor of the PLL circuit.
00: ×1
01: ×2
10: ×4
11: Setting prohibited
Rev. 1.00 Jan. 24, 2008 Page 455 of 534
REJ09B0426-0100