HD74SSTV32852 Datasheet, PDF (5/9 Pages) Renesas Technology Corp – 24-bit to 48-bit Registered Buffer with SSTL_2 Inputs and Outputs

HD74SSTV32852
Switching Characteristics
Item
Clock frequency ^*1
Setup time
Fast slew rate ^{*4, 6}
Slow slew rate ^{*5, 6}
Hold time
Fast slew rate ^{*4, 6}
Slow slew rate ^{*5, 6}
Differential inputs active time
Differential inputs inactive time
Pulse width
Output slew ^*3
Symbol
f_clock
t_su
t_h
t_act
V_CC = 2.5 ± 0.2 V
Min
Max
—
200
0.75
—
0.9
—
0.75
—
0.9
—
22
—
t_inact
22
—
t_w
2.5
—
t_SL
1
4
Unit
Test Condition
MHz
ns Data before CLK↑, CLK↓
ns Data after CLK↑, CLK↓
ns
ns
ns
volt/ns
Data inputs must be low after
RESET high.
Data and clock inputs must be held
at valid levels (not floating) after
RESET low.
CLK, CLK “H” or “L”
(C_L = 30 pF, R_L = 50 Ω, V_REF = V_TT = V_DDQ × 0.5)
Item
Symbol
V_CC = 2.5 ± 0.2 V
Unit
Min
Typ
Max
FROM
(Input)
TO
(Output)
Maximum clock frequency
f_max
200
—
—
MHz
Propagation delay time ^*2
t_PLH, t_PHL
1.1
—
3.1
ns CLK, CLK
QA, QB
t_PHL
—
—
5.0
RESET
QA, QB
Notes: 1. Although the clock is differential, all timing is relative to CLK going high and CLK going low.
2. This timing relationship is specified into test load (see waveforms – 3, 4) with all of the outputs switching.
3. Assumes into an equivalent, distributed load to the address net structure defined in the application
information provided in this specification.
4. For data signal input slew rate ≥ 1 V/ns.
5. For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns.
6. CLK, CLK signals input slew rates are ≥ 1 V/ns.
Rev.4.00 Apr 07, 2006 page 5 of 8